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MPC8540 bảng dữ liệu(PDF) 198 Page - Freescale Semiconductor, Inc |
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MPC8540 bảng dữ liệu(HTML) 198 Page - Freescale Semiconductor, Inc |
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198 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 4-12 Freescale Semiconductor Reset, Clocking, and Initialization • POR PLL status register (PORPLLSR) • POR boot mode status register (PORBMSR) • POR I/O impedance status and control register (PORIMPSCR) • POR device status register (PORDEVSR) • POR debug mode status register (PORDBGMSR) • General-purpose POR configuration register (GPPORCR)—reports the value on LAD[0:31] during POR (can be used to external system configuration) NOTE In the following tables, the binary value 0b0 represents a signal pulled down to GND and a value of 0b1 represents a signal pulled up to VDD, regardless of the sense of the functional signal name on the signal. 4.4.3.1 System PLL Ratio The system PLL inputs, shown in Table 4-9, establish the clock ratio between the PCI_CLK/SYSCLK input and the platform clock used by the MPC8540. The platform clock, also called the CCB clock, drives the L2 cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB). There is no default value for this PLL ratio; these signals must be pulled to the desired values. Note that the values latched on these signals during POR are accessible in the PORPLLSR (POR PLL status register), as described in Section 18.4.1.1, “POR PLL Status Register (PORPLLSR).” |
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