MPC8540 datasheet(187/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-1

Chapter 4

Reset, Clocking, and Initialization

This chapter describes the reset, clocking, and some overall initialization of the MPC8540,

including a definition of the reset configurations signals and the options they select. Additionally,

the configuration, control, and status registers are described. Note that chapters in this book

describe specific initialization aspects for individual blocks.

4.1

Overview

The reset, clocking, and control signals provide many options for the operation of the MPC8540.

Additionally, many modes are selected with reset configuration signals during the assertion of a

hard reset (assertion of HRESET).

4.2

External Signal Descriptions

Table 4-1 summarizes the external signals described in this chapter. Table 4-2 and Table 4-3 have

detailed signal descriptions, but Table 4-1 contains references to additional sections that contain

more information.

The following sections describe the reset and clock signals in detail.

Table 4-1. Signal Summary

Signal

I/O

Description

References

(Section/Page)

HRESET

Hard reset input. Causes a power-on reset (POR) sequence

4.4.1.2/4-9

HRESET_REQ

Hard reset request output. An internal block requests that

HRESET be asserted

—

SRESET

Soft reset input. Causes mcp assertion to the core

4.4.1.1/4-9

READY

The MPC8540 has completed the reset operation and is not in a

power-down (nap, doze or sleep) or debug state.

4.4.2/4-9

SYSCLK

Primary clock input to the MPC8540

4.4.4.1/4-23

RTC

Real time clock input

4.4.4.4/4-25

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