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Hardware Implementation-Dependent Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-27

6.10 Hardware Implementation-Dependent Registers

6.10.1 Hardware Implementation-Dependent Register 0 (HID0)

Field EMCP

—

DOZE NAP SLEEP

—

TBEN

SEL_TBCLK

—

NOPTI

Reset

All zeros

R/W

SPR

SPR 1008

Figure 6-31. Hardware Implementation-Dependent Register 0 (HID0)

Table 6-16. HID0 Field Descriptions

Bits

Name

Description

EMCP

Enable machine check pin, MCP. Used to mask out further machine check exceptions caused by

assertion of MCP.

0MCP is disabled.

1MCP is enabled. If MSE[ME] = 0, asserting MCP causes checkstop. If MSR[ME] = 1, asserting MCP

causes a machine check exception.

33–39

—

Reserved, should be cleared.

DOZE

Doze power management mode. If MSR[WE] is set, this bit controls DOZE mode.

0 Core not in doze mode

1 Core in doze mode

NAP

Nap power management mode. If MSR[WE] is set, this bit controls NAP mode.

0 Core not in nap mode

1 Core in nap mode

SLEEP

Configure for sleep power management mode. Controls SLEEP mode if MSR[WE] is set.

0 Core not in sleep mode

1 Core in sleep mode

43–48

—

Reserved, should be cleared.

TBEN

Time base enable

0 Time base disabled (no counting)

1 Time base enabled

• If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 0, the time base is updated every 8 bus clocks

• If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 1, the time base is updated on the rising edge of

core_TBCLK (sampled at bus rate). The maximum supported frequency can be found in the electrical

specifications, but this value is approximately 25% of the bus clock frequency.

SEL_TBCL

Select time base clock. If the time base is enabled, this field functions as follows:

0 Time base is based on the processor clock

1 Time base is based on the TBCLK (RTC) input

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