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STM32H753II bảng dữ liệu(PDF) 271 Page - STMicroelectronics

tên linh kiện STM32H753II
Giải thích chi tiết về linh kiện  32-bit Arm® Cortex®-M7 480MHz MCUs, 2MB Flash,1MB RAM, 46 com. and analog interfaces, crypto
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STM32H753II bảng dữ liệu(HTML) 271 Page - STMicroelectronics

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DS12117 Rev 8
271/360
STM32H753xI
Electrical characteristics (rev V)
318
7.3.18
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 180 and Table 181 for QUADSPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 121: General operating conditions, with the
following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
The following table summarizes the parameters measured in SDR mode.
Table 179. LPSDR SDRAM Write timings(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
ns
td(SDCLKL _Data)
Data output valid time
-
2.5
th(SDCLKL _Data)
Data output hold time
0
-
td(SDCLKL_Add)
Address valid time
-
2.5
td(SDCLKL-SDNWE)
SDNWE valid time
-
2.5
th(SDCLKL-SDNWE)
SDNWE hold time
0
-
td(SDCLKL- SDNE)
Chip select valid time
-
3
th(SDCLKL- SDNE)
Chip select hold time
0
-
td(SDCLKL-SDNRAS)
SDNRAS valid time
-
1.5
th(SDCLKL-SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL-SDNCAS)
SDNCAS valid time
-
1.5
td(SDCLKL-SDNCAS)
SDNCAS hold time
0
-



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