STM32H753II datasheet(195/361 Pages) STMICROELECTRONICS

195 / 361 page

DS12117 Rev 8

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STM32H753xI

Electrical characteristics (rev Y)

318

SAI characteristics

Unless otherwise specified, the parameters given in Table 107 for SAI are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 23: General operating conditions, with the following

configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C=30 pF

•

Measurement points are performed at CMOS levels: 0.5VDD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate

function characteristics (SCK,SD,WS).

Table 107. SAI characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fMCK

SAI Main clock output

256 x 8K

256xFs

MHz

FCK

SAI clock frequency(2)

Master data: 32 bits

128xFs(3)

MHz

Slave data: 32 bits

128xFs

tv(FS)

FS valid time

Master mode

2.7≤VDD≤3.6V

-15

Master mode

1.71≤VDD≤3.6V

-20

tsu(FS)

FS setup time

Slave mode

th(FS)

FS hold time

Master mode

Slave mode

tsu(SD_A_MR)

Data input setup time

Master receiver

0.5

tsu(SD_B_SR)

Slave receiver

th(SD_A_MR)

Data input hold time

Master receiver

3.5

th(SD_B_SR)

Slave receiver

tv(SD_B_ST)

Data output valid time

Slave transmitter (after enable edge)

2.7≤VDD≤3.6V

-17

Slave transmitter (after enable edge)

1.62≤VDD≤3.6V

-20

th(SD_B_ST)

Data output hold time

Slave transmitter (after enable edge)

tv(SD_A_MT)

Data output valid time

Master transmitter (after enable edge)

2.7≤VDD≤3.6V

-17

Master transmitter (after enable edge)

1.62≤VDD≤3.6V

-20

th(SD_A_MT)

Data output hold time

Master transmitter (after enable edge)

7.55

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

3. With FS=192 kHz.

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