LTC1760CFW datasheet(37/44 Pages) LINER

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LTC1760

sn1760 1760is

Input and Output Capacitors

In the 4A Lithium Battery Charger (Typical Application

section), the input capacitor (CIN) is assumed to absorb all

input switching ripple current in the converter, so it must

have adequate ripple current rating. Worst-case RMS

ripple current will be equal to one half of output charging

current. Actual capacitance value is not critical. Solid

tantalum low ESR capacitors have high ripple current

rating in a relatively small surface mount package,

but

caution must be used when tantalum capacitors are used

for input or output bypass. High input surge currents can

be created when the adapter is hot-plugged to the charger

or when a battery is connected to the charger. Solid

tantalum capacitors have a known failure mechanism

when subjected to very high turn-on surge currents. Only

Kemet T495 series of “Surge Robust” low ESR tantalums

are rated for high surge conditions such as battery to

ground.

The relatively high ESR of an aluminum electrolytic for

C15, located at the AC adapter input terminal, is helpful in

reducing ringing during the hot-plug event. Refer to AN88

for more information.

Highest possible voltage rating on the capacitor will mini-

mize problems. Consult with the manufacturer before use.

Alternatives include new high capacity ceramic (at least

µF) from Tokin, United Chemi-Con/Marcon, et al. Other

alternative capacitors include OSCON capacitors from

Sanyo.

The output capacitor (COUT) is also assumed to absorb

output switching current ripple. The general formula for

capacitor current is:

IRMS =

(L1)(f)

VBAT

VDCIN

()

0.29 (VBAT) 1 –

APPLICATIO S I FOR ATIO

Then the equation to extract C7 is:

REF

ISET

SET

∑

•

∆

= 0.8/0.01/18.77k(10

µs) ≅ 0.043µF

In order to prevent overshoot during start-up transients

the time constant associated with C7 must be shorter than

the time constant of C5 at the ITH pin. If C7 is increased to

improve ripple rejection, then C5 should be increased

proportionally and charger response time to average cur-

rent variation will degrade.

Capacitors CB1 and CB2 are used to filter the VDAC delta-

sigma modulation frequency components to a level which

is essentially DC. CB2 is the primary filter capacitor and

CB1 is used to provide a zero in the response to cancel the

pole associated with CB2. Acceptable voltage ripple at VSET

is about 10mVP-P. Since the period of the delta-sigma

switch closure, T∆Σ, is about 11µs and the internal VDAC

resistor, RVSET, is 7.2kΩ, the ripple voltage can be ap-

proximated by:

∆

VSET

REF

VSET

()

∑

•

Then the equation to extract CB1 || CB2 is:

REF

VSET

•

∑

∆

CB2 should be 10× to 20× CB1 to divide the ripple voltage

present at the charger output. Therefore CB1 = 0.01µF and

CB2 = 0.1µF are good starting values. In order to prevent

overshoot during start-up transients the time constant

associated with CB2 must be shorter than the time constant

of C5 at the ITH pin. If CB2 is increased to improve ripple

rejection, then C5 should be increased proportionally and

charger response time to voltage variation will degrade.

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