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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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K4X51163PC bảng dữ liệu(PDF) 13 Page - Samsung semiconductor |
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K4X51163PC bảng dữ liệu(HTML) 13 Page - Samsung semiconductor |
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13 / 23 page  K4X51163PC - L(F)E/G February 2006 Mobile-DDR SDRAM AC Timming Parameters & Specifications Parameter Symbol DDR266 DDR222 Unit Note Min Max Min Max Clock cycle time CL=2 tCK 12.0 15.0 ns CL=3 7.5 9.0 Row cycle time tRC 67.5 81 ns Row active time tRAS 45 70,000 54 70,000 ns RAS to CAS delay tRCD 22.5 27 ns Row precharge time tRP 22.5 27 ns Row active to Row active delay tRRD 15 15 ns Write recovery time tWR 15 15 ns Last data in to Active delay tDAL 2tCK+tRP 2tCK+tRP - 2 Last data in to Read command tCDLR 1 1 tCK Col. address to Col. address delay tCCD 1 1 tCK Clock high level width tCH 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 tCK DQ Output data access time from CK/ CK CL=2 tAC 2 8 2.5 8 ns 3 CL=3 2 6 2.5 6 DQS Output data access time from CK/CK CL=2 tDQSCK 2 8 2.5 8 ns CL=3 2 6 2.5 6 Data strobe edge to ouput data edge tDQSQ 0.6 0.7 ns Read Preamble CL=2 tRPRE 0.5 1.1 0.5 1.1 tCK CL=3 0.9 1.1 0.9 1.1 Read Postamble tRPST 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 ns 4 DQS-in hold time tWPREH 0.25 0.25 tCK DQS-in high level width tDQSH 0.4 0.6 0.4 0.6 tCK DQS-in low level width tDQSL 0.4 0.6 0.4 0.6 tCK DQS falling edge to CK setup time tDSS 0.2 0.2 tCK DQS falling edge hold time from CK tDSH 0.2 0.2 tCK DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 tCK Address and Control Input setup time tIS 1.3 1.5 ns 1 Address and Control Input hold time tIH 1.3 1.5 ns 1 Address & Control input pulse width tIPW 2.6 3.0 1 DQ & DM setup time to DQS tDS 0.8 1.1 ns 5,6 DQ & DM hold time to DQS tDH 0.8 1.1 ns 5,6 DQ & DM input pulse width tDIPW 1.8 2.4 ns DQ & DQS low-impedence time from CK/CK tLZ 1.0 1.0 ns DQ & DQS high-impedence time from CK/CK tHZ 6.0 7.0 ns DQS write postamble time tWPST 0.4 0.6 0.4 0.6 tCK DQS write preamble time tWPRE 0.25 0.25 tCK |
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