ST7293C3B6 datasheet(23/69 Pages) STMICROELECTRONICS

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ST7294

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4.2 I/O PORTS

4.2.1 Functional Description

Ports A and B are 8-bit I/O ports, port C is a 6-bit

I/O port. Each of their pins may be individually con-

figured under software control as either input or out-

put.

Each bit of any Data Direction Register corre-

sponds to an I/O pin on the associated port. A bit

must be set to configure its associated pin as out-

put and must be cleared to configure its associat-

ed pin as input. The Data Direction Registers can

be written or read.

The typical I/O circuit is shown on Figure 17. Any

write to an I/O port updates the port output register

even if it is configured as input. Any read of an I/O

port returns either the data latched in the port out-

put register (output configured pins) or the value

at the I/O pin (input configured pins) (see Table 7).

At power-on or external reset, all DDR’s are

cleared, which configures all port A, B and C pins

as inputs, but the port output registers are not ini-

tialized. Thus, the I/O port should be written before

setting the DDR bits to avoid undefined levels.

Depending on the chosen mask option, Port A bits

can be defined as an Input/Output line or as an In-

put/Output drain line. When programmed as input,

each port line may be tied to V

DD through an inter-

nal pull-up resistor (by option).

Depending on the chosen mask option, PORT B

bits can be tied to V

DD through an internal pull-up

resistor if defined as input.

Depending on the chosen mask option, PORT C

bits can be configured as wake-up interrupt input

with an internal pull-up resistor. To enter this

mode, the corresponding bit in DDR must be set to

1 and the corresponding bit in DR must be set to

0.This mode can only be reached for PC0 and

PC1 if they have not been configured as ICAP or

OCMP1 respectively.

All unused I/O lines should be tied to an appropri-

ate logic level (either V

DD or VSS).

Figure 17. Typical I/O pin configuration of Ports A and C

DATA DIRECTION

BIT

LATCHED

OUTPUT DATA

BIT

INPUT

BIT

INPUT

I/O

OUTPUT

INTERNAL

CONNECTIONS

DDR 7

DDR 6

DDR 5

DDR 4

DDR 3

DDR 2

DDR 1

DDR 0

P-7

P-6

P-5

P-4

P-3

P-2

P-1

P-0

TYPICAL PORT

DATA DIRECTION

TYPICAL PORT

I/O

REG.

VR000084

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