STAC9460 datasheet(9/21 Pages) ETC1

9 / 21 page

2-9460-D1-1-0-0801

STAC9460/62

Two and Six-Channel, 24-Bit, 192 kHz Audio Codec

PRELIMINARY

INFORMATION

8/2 4 /0 1

5. SERIAL INTERFACE

Below is the figure for the serial interface between the STAC9460/62 and a

µC or

µP. All register settings and chip control are performed via this serial interface,

except for the address LSB.

Note: This functions as a standard 2-wire I2C compatible interface, however, the CS

(chip select) line offers address flexibility and must be either hard wired to ground or

tied to Vdd if no other chips are connected to the bus. Refer to Table 7.1.1 on page 14

for additional information.

5.1.

Clocking

The STAC9460/62 derives its clock from an externally connected clock through the

MCLK pin in combination with the Master CLocking Register, which is further

explained in section 7.1.9.

5.2.

Reset

There are two types of resets as detailed below:

•

A hard reset is achieved by driving the reset line low

•

A soft reset is achieved by writing to the Reset/Status register (00h)

By writing to the Reset/Status Register (00h) a reset for the Address Control Regis-

ter will occur. Writing any value to this register performs a register reset, which

causes all registers to revert to their default values. This soft reset will also place the

I2C state machine in a "stop" condition, and will not continue to auto-increment

through the address space. Additional information about the Address Control Reg-

ister can be found in section 7.1.12.

µC /µ P

S T A C 94 60

SD AT A

SCLK

MC LK

Figure 3. Serial interface to microcontroller or microprocessor

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