NAND04GR3B datasheet(18/59 Pages) STMICROELECTRONICS

18 / 59 page

NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B

18/59

COMMAND SET

All bus write operations to the device are interpret-

ed by the Command Interface. The Commands

are input on I/O0-I/O7 and are latched on the rising

edge of Write Enable when the Command Latch

Enable signal is high. Device operations are se-

lected by writing specific commands to the Com-

mand

The

two-step

command

sequences for program and erase operations are

imposed to maximize data security.

The

Commands

are

summarized

Table

10., Commands.

Table 10. Commands

Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.

2. For consecutive read operations the 00h command does not need to be repeated.

3. Only during Cache Read busy.

Command

Bus Write Operations(1)

Commands

accepted

during busy

1st CYCLE

2nd CYCLE

3rd CYCLE

4th CYCLE

Read

00h(2)

30h

–

Random Data Output

05h

E0h

–

Cache Read

00h

31h

–

Exit Cache Read

34h

–

Yes(5)

Page Program

(Sequential Input default)

80h

10h

–

Random Data Input

85h

–

Copy Back Program

00h

35h

85h

10h

Cache Program

80h

15h

–

Block Erase

60h

D0h

–

Reset

FFh

–

Yes

Read Electronic Signature

90h

–

Read Status Register

70h

–

Yes

Read Block Lock Status

7Ah

–

Blocks Unlock

23h

24h

–

Blocks Lock

2Ah

–

Blocks Lock-Down

2Ch

–

NAND04GR3B bảng dữ liệu(PDF) 18 Page - STMicroelectronics

NAND04GR3B bảng dữ liệu(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

bảng dữ liệu tải về

Link URL