PI3DPX1203

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February 2021

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PI3DPX1203

Document number DS40598 Rev 2-2

4.2 Function Description

4.2.1 Power-up Timing

After PRSNT# signal is properly set, power up timing sequence complete. PRSNT signal from controller must be low until power sup-

ply become stable.

>100µS Delay time

<10mS Ramp-up time

<1ns

Power Supply

PRSNT from Controller

PRSNT# pin

Signal Output

10%

90%

0.7VDD

Normal Operation

Internal

Pull-up

Active Low

Figure 4-1 Power-up timing Sequence

4.2.2 Reset Implementation

When PRSNT# is high, the device is power-down mode and outputs are high impedance. It is critical to transition the PRSNT# , after

the power supply VDD has reached the minimum recommended operation voltage. This can be achieved by the control signal GPO or

by an external capacitor connected to GND.

To insure properly reset, the PRSNT# pin must be de-asserted for at least 100μS before re-asserted, and must be reprogrammed in I2C

mode. When using external capacitor, the size of the cap value depends on the power-up VDD supply ramp. Larger value results in a

slower ramp-up time. Consider 0.1uF capacitor is recommended as a reasonable first estimate.

100k-Ohm

VDD

PRSNT#

100k-Ohm

VDD

C

C

PRSNT#

GPO

External Capacitor Controlled

GPO pin contolled from Controller IC

Figure 4-2 Reset Control from External Capacitor or GPO pin