2

ATtiny22L

allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC

microcontrollers.

Block Diagram

Figure 1. The ATtiny22L Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

REGISTER

TIMER/

COUNTER

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA REGISTER

PORTB

PROGRAMMING

LOGIC

TIMING AND

CONTROL

INTERRUPT

UNIT

EEPROM

SPI

STATUS

REGISTER

Z

Y

X

ALU

PORTB DRIVERS

PB0 - PB4

RESET

VCC

GND

CONTROL

LINES

8-BIT DATA BUS