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LM91DIMQAX bảng dữ liệu(PDF) 5 Page - OKI electronic componets |
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LM91DIMQAX bảng dữ liệu(HTML) 5 Page - OKI electronic componets |
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5 / 14 page ![]() Logic Electrical Characteristics DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for V CC=+3.0 to 3.6 Vdc. Boldface limits apply for TA =TJ =TMIN to T MAX; all other limits TA=TJ=+25˚C, unless otherwise noted. Symbol Parameter Conditions Typical LM91D Units (Note 6) Limits (Note 7) (Limit) SMBData, SMBCLK V IN(1) Logical “1” Input Voltage 2.1 V (min) V IN(0) Logical “0”Input Voltage 0.8 V (max) I IN(1) Logical “1” Input Current V IN =VCC 0.005 1.0 µA (max) I IN(0) Logical “0” Input Current V IN = 0V −0.005 −1.0 µA (max) ADD0, ADD1 V IN(1) Logical “1” Input Voltage V CC 1.6 V (min) V IN(0) Logical “0”Input Voltage GND 0.5 V (max) I IN(1) Logical “1” Input Current V IN =VCC 50 600 µA (max) I IN(0) Logical “0” Input Current V IN =0V 50 600 µA (max) ALL DIGITAL INPUTS C IN Input Capacitance 20 pF ALL DIGITAL OUTPUTS I OH High Level Output Current V OH =VCC 100 µA (max) V OL SMBus Low Level Output Voltage I OL =3 mA I OL =6 mA 0.4 0.6 V (max) SMBus DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for V CC=+3.0 Vdc to +3.6 Vdc, CL (load capacitance) on output lines = 80 pF. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = +25˚C, unless otherwise noted. The switching characteristics of the LM91 fully meet or exceed the published specifications of the SMBus or I 2C bus. The fol- lowing parameters are the timing relationships between SMBCLK and SMBData signals related to the LM91. They are not nec- essarily the I 2C or SMBus bus specifications. Symbol Parameter Conditions Typical Limits Units (Note 6) (Note 7) (Limit) f SMB SMBus Clock Frequency 400 10 kHz (max) kHz (min) t LOW SMBus Clock Low Time 10% to 10% 1.3 25 µs (min) ms (max) t LOWSEXT Cumulative Clock Low Extend Time 25 ms (max) t HIGH SMBus Clock High Time 90% to 90% 0.6 µs (min) t R;SMB SMBus Rise Time 10% to 90% 1 µs t F;SMB SMBus Fall Time 90% to 10% 0.3 µs t OF Output Fall Time C L = 400 pF I O =3 mA 250 ns (max) t TIMEOUT SMBData and SMBCLK Time Low for Reset of Serial Interface (Note 12) 25 40 ms (min) ms (max) t 1 SMBCLK (Clock) Period 2.5 µs (min) t 2, t SU;DAT Data In Setup Time to SMBCLK High 100 ns (min) t 3, t HD;DAT Data Out Stable after SMBCLK Low 0 0.9 ns (min) µs (max) t 4, t HD;STA SMBData Low Setup Time to SMBCLK Low 100 ns (min) t 5, t SU;STO SMBData High Delay Time after SMBCLK High (Stop Condition Setup) 100 ns (min) t 6, t SU;STA SMBus Start-Condition Setup Time 0.6 µs (min) www.national.com 5 |
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