LT4293 datasheet(39/44 Pages) AD

39 / 44 page

LTC9101-2/LTC9102

Rev. 0

For more information www.analog.com

LAYOUT REQUIREMENTS

Strict adherence to board layout, parts placement and

routing requirements is critical for IEEE compliance, para-

metric measurement accuracy, system robustness and

thermal dissipation. Refer to the DC3160A-KIT demo kit

for example layout references.

Kelvin Sense

Proper connection of the port current Kelvin sense lines is

important for current threshold accuracy and IEEE compli-

ance. Refer to Figure 31 for an example layout of these Kelvin

sense lines. The LTC9102 VSSKn pin is Kelvin connected to

the sense resistor (VEE side) pad and is not otherwise con-

nected to VEE copper areas. Similarly, the LTC9102 SENSEn

pin is Kelvin connected to the sense resistor (SENSEn side)

pad and is not otherwise connected in the power path.

Figure 31 shows the two Kelvin traces from the LTC9102 to

the sense resistor (RSENSEn).

High-Speed Data Interface

The LTC9101-2/LTC9102 chipset communicates across

a proprietary high-speed, multi-drop data interface.

This allows for a single LTC9101-2 to control up to

four LTC9102s.

TO FET(Qn)

VEE

RSENSEn

SENSEn

VSSKn

9101-2 F31

Figure 31. RSENSE Kelvin Connections

The data-lines require impedance matched traces to each

LTC9102. The data bus termination resistors must be located

at the LTC9102 farthest away from the isolation transform-

ers. For isolated applications, the DC biasing resistors must

connect to the LTC9102 CAP3 pin, farthest away from the

isolation transformers. As shown in Figure 28 and Figure 29,

design the interface with 100Ω differential transmission lines,

and terminate 100Ωs differentially. Limit the high-speed

data interface line length to 16 inches. Minimize the trans-

mission stubs between the LTC9102s and the high-speed

data interface.

APPLICATIONS INFORMATION

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