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CYWUSB6935
Document #: 38-16008 Rev. *C
Page 21 of 33
Addr: 0x38
REG_SYN_LOCK_CNT
Default: 0x64
7
654
3210
Count
Figure 7-31. Synthesizer Lock Count
Bit
Name Description
7:0
Count Determines the length of delay in 2-µs increments for the synthesizer to lock when auto synthesizer is enabled via Control
register (0x03, bit 1=0) and not using the PLL lock signal. The default register setting is typically sufficient.
Addr: 0x3C-3F
REG_MID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
987654
3210
Address 0x3F
Address 0x3E
Address 0x3D
Address 0x3C
Figure 7-32. Manufacturing ID
Bit
Name
Description
31:30 Address[31:30] These bits are read back as zeroes.
29:0
Address[29:0]
These bits are the Manufacturing ID (MID) for each IC. The contents of these bits cannot be read unless the MID
Read Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the Manufacturing ID register (Reg
0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only
be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). This register is read-only.
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