FSCM0565R datasheet(13/24 Pages) ONSEMI

13 / 24 page

Functional Description

1. Startup: At startup, an internal high-voltage current

source supplies the internal bias and charges the

external capacitor (Ca) connected to the VCC pin, as

illustrated in Figure 23. When VCC reaches 12V, the

power switch begins switching and the internal

high-voltage current source is disabled. The

power

switch continues its normal switching operation and

the power is supplied from the auxiliary transformer

winding unless VCC goes below the stop voltage of 8V.

Figure 23. Startup Circuit

Feedback Control: power switch employs current-mode

control, as shown in Figure 24. An opto-coupler (such as

the FOD817A) and shunt regulator (such as the KA431)

are typically used to implement the feedback network.

Comparing the feedback voltage with the voltage across

the Rsense resistor makes it possible to control the

switching duty cycle. When the reference pin voltage of

the shunt regulator exceeds the internal reference

voltage of 2.5V, the opto-coupler LED current increases,

pulling down the feedback voltage and reducing the duty

cycle. This typically happens when the input voltage is

increased or the output load is decreased.

Figure 24. Pulse-Width-Modulation (PWM) Circuit

2.1 Pulse-by-Pulse Current Limit: Because current-

mode control is employed, the peak current through the

SenseFET is limited by the inverting input of PWM

comparator (VFB*), as shown in Figure 24. Assuming

that the 0.9mA current source flows only through the

internal resistor (3R + R = 2.8k), the cathode voltage of

diode D2 is about 2.5V. Since D1 is blocked when the

feedback voltage (VFB) exceeds 2.5V, the maximum

voltage of the cathode of D2 is clamped at this voltage,

clamping VFB*. Therefore, the peak value of the current

through the SenseFET is limited.

2.2 Leading-Edge Blanking (LEB): At the instant the

internal SenseFET is turned on, a high-current spike

usually occurs through the SenseFET, caused by

primary-side capacitance and secondary-side rectifier

reverse recovery. Excessive voltage across the Rsense

resistor would lead to incorrect feedback operation in the

current-mode PWM control. To counter this effect, the

power switch employs a leading-edge blanking (LEB)

circuit. This circuit inhibits the PWM comparator for a

short time (tLEB) after the SenseFET is turned on.

3. Synchronization: The FSQ-series employs a quasi-

resonant switching technique to minimize the switching

noise and loss. The basic waveforms of the quasi-

resonant converter are shown in Figure 25. To minimize

the MOSFET's switching loss, the MOSFET should be

turned on when the drain voltage reaches its minimum

value, which is indirectly detected by monitoring the VCC

winding voltage, as shown in Figure 25.

Figure 25. Quasi-Resonant Switching Waveforms

8V/12V

VREF

Internal

Bias

VCC

VSTR

Istart

Vcc good

VDC

CVCC

FSQ0565 Rev.00

OSC

VCC

VREF

Idelay

IFB

VSD

Gate

driver

OLP

VFB*

VFB

KA431

H11A817A

Rsense

SenseFET

FSQ0565 Rev.00

VDC

VRO

Vds

1.2V

Vsync

230ns Delay

1.0V

Vovp (8V)

MOSFET Gate

FSQ0565 Rev.00

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