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K4M561633G-RBL bảng dữ liệu(PDF) 8 Page - Samsung semiconductor

tên linh kiện K4M561633G-RBL
Giải thích chi tiết về linh kiện  4M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
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nhà sản xuất  SAMSUNG [Samsung semiconductor]
Trang chủ  http://www.samsung.com/Products/Semiconductor
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K4M561633G-RBL bảng dữ liệu(HTML) 8 Page - Samsung semiconductor

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K4M561633G - R(B)N/G/L/F
January 2006
Mobile SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Symbol
-75
-1H
-1L
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
tCC
7.5
1000
9.0
1000
9.0
1000
ns
1
CLK cycle time
CAS latency=2
tCC
9.0
9.0
12
CLK cycle time
CAS latency=1
tCC
-
-
25
CLK to valid output delay
CAS latency=3
tSAC
5.4
7
7
ns
1,2
CLK to valid output delay
CAS latency=2
tSAC
7
7
8
CLK to valid output delay
CAS latency=1
tSAC
-
-
20
Output data hold time
CAS latency=3
tOH
2.5
2.5
2.5
ns
2
Output data hold time
CAS latency=2
tOH
2.5
2.5
2.5
Output data hold time
CAS latency=1
tOH
-
-
2.5
CLK high pulse width
tCH
2.5
3.0
3.0
ns
3
CLK low pulse width
tCL
2.5
3.0
3.0
ns
3
Input setup time
tSS
2.0
2.5
2.5
ns
3
Input hold time
tSH
1.0
1.0
1.0
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
ns
2
CLK to output in Hi-Z
CAS latency=3
tSHZ
5.4
7
7
ns
CAS latency=2
7
7
8
CAS latency=1
-
-
20



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