iC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 7/9
DESCRIPTION OF FUNCTIONS
Normal operation
Following an internal power-on reset the integration
and hold capacitors are discharged and the sample
and hold circuit is set to sample mode. A high signal
at SI anda rising edge at CLK triggers a readout cycle
and with it a new integration cycle.
In this process the hold capacitors of pixels 1 to 127
are switched to hold mode immediately (SNH = 1),
with pixel 128 (SNH128 = 1) following suit one clock
pulse later. This special procedure allows all pixels to
be read out with just 128 clock pulses. The integration
capacitors are discharged by a one clock long reset
signal (NRCI= 0) which occurs between the2nd and
3rd falling edge of the readout clock pulse (cf. Figure
4). After the 127 pixels have been read out these are
again set to sample mode (SNH = 0), likewise for pixel
128 one clock pulse later (SNH128 = 0).
Figure 4: Readout cycle and integration sequence
If prior to the 128th clock pulse a high signal occurs
at SI the present readout is halted and immediately
reinitiated with pixel 1. In this instance the hold ca-
pacitors retain their old value i.e. hold mode prevails
(SNH/SNH128 = 0).
Figure 5: Restarting a readout cycle
With more than 128 clock pulses until the next SI sig-
nal, pixel1 is output without entering hold mode; the
output voltage tracks the voltage of the pixel1 integra-
tion capacitor.
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