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CS43198 bảng dữ liệu(PDF) 49 Page - Cirrus Logic

tên linh kiện CS43198
Giải thích chi tiết về linh kiện  130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
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CS43198 bảng dữ liệu(HTML) 49 Page - Cirrus Logic

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DS1156F1
49
CS43198
4.10 DSD and PCM Mixing
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index) at
full-rated performance. When 0 dB-SACD and 0 dBFS PCM need to be level matched, DSD_ZERODB must be set. In this
mode, signals of +3-dB SACD may be applied for brief periods of time; however, performance at these levels is not
guaranteed. If sustained levels approaching +3-dB SACD levels are required, DSD_ZERODB must be cleared, which
matches a +3-dB SACD output level. DSD_ZERODB does not affect volume in Direct DSD mode.
Figure 4-26. DSD Phase Modulation Mode Diagram
4.10 DSD and PCM Mixing
For mobile application, the CS43198 provides a feature for mixing in PCM notification during DSD playback, with the setup
in Table 4-10.
It is assumed that the DSD path has been properly configured for DSD playback. Note that the mixing feature is not
applicable for Direct DSD playback.
During normal DSD playback, the ASP can be shut down. At the PCM notification event, the ASP must be properly
configured to receive PCM samples at 44.1 kHz. After the ASP subclocks are running, set MIX_PCM_PREP to indicate to
the CS43198 that the PCM mixing event is imminent. After 1.6 ms, MIX_PCM_DSD can be safely set to initiate the mixing
process. After the PCM notification mixing is complete, clear both MIX_PCM_DSD and MIX_PCM_PREP at the same
time. If desired, the ASP can be shut down to save power.
Table 4-10. Mixing Configurations Supported by the CS43198
PCM Input Configuration
DSD Input Configuration
I2S or TDM on
ASP
44.1 kHz
Master
DSD on DSD IF
2.8224, 5.6448, or
11.2896 MHz on
DSDCLK
Master
Slave 1
1.The ASP/XSP subclocks and DSDCLK are required to be synchronous.
Slave 1
Master
DoP on XSP
176.4 or 352.8 kHz
Master
Slave 1
Slave 1
DSDA,
DSDB
D1
D0
D2
DSDCLK
DSD Normal Mode
(128•Fs
or
256•Fs)
D1
D1
D2
D0
DSDCLK =
BCKD
DSDA,
DSDB
(64•Fs
or
128•Fs)
DSD Phase
Modulation Mode
(64•Fs,
128•Fs, or
256•Fs)
DSDCLK =
BCKA
(DSD_PM_EN = 0)
(DSD_PM_EN = 1)
(DSD_PM_SEL = 0)
(DSD_PM_SEL = 1)



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