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CS43131 bảng dữ liệu(PDF) 62 Page - Cirrus Logic

tên linh kiện CS43131
Giải thích chi tiết về linh kiện  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
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CS43131 bảng dữ liệu(HTML) 62 Page - Cirrus Logic

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DS1155F1
CS43131
4.14 Programmable Filter
4.14 Programmable Filter
In the CS43131, there are a series of programmable filters which is open for user's customization. The filter coefficients
can be programmed for altering frequency response or other characteristics to fit the design intention. The filter runs at the
input sample rate as set by xSP. This feature is intended to be used for normal PCM playback under single-, double-, and
quad-speed settings. (If operating at 192 kHz, MCLK_INT is required to be at 24.576 MHz.) For WBF mode and impedance
measurement mode, the filter should be properly turned off.
The filter series are composed of 1 first-order IIR system (FOS) and 3 second-order IIR system (SOS), which effectively
is a seventh-order system. FOS and SOS structures are illustrated as in Fig. 4-35 and Fig. 4-36, respectively. Any filter
stage can be chosen to be either utilized or bypassed through coefficient settings. Each stage is represented by filter
coefficients, which is accessed through I2C writes. The filter coefficients are located in register address 0x09 000C to
0x09 0041. Each coefficient is comprised of a most-significant byte, a least-significant byte, and a sign byte.
Figure 4-35. First-Order IIR System
Figure 4-36. Second-Order IIR System
The filter can only be programmed when PDN_HP is set. Program the filter coefficients when PDN_HP is cleared will result
in non-expected behavior.
To properly enable each filter's coefficients, after the coefficients is programmed in control port, user enable the control
port filter coefficients through registers Programmable Filter Control 1 and Programmable Filter Control 2. When user not
using the programmable filters, the filter should be disabled properly.
Z
‐1
b0
b1
‐a1
X[n]
Y[n]
+
+
Z
‐1
X[n]
Y[n]
Z
‐1
+
+
+
‐a2
‐a1
b0
b1
b2
+



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