ADC083000 datasheet(32/33 Pages) NSC

32 / 33 page

2.0 Applications Information

(Continued)

TABLE 8. Non-Extended Control Mode Operation (Pin

14 High or Low)

Low

High

Floating

0.50 V

P-P

Output

0.70 V

P-P

Output

n/a

OutEdge =

Neg

OutEdge =

Pos

DDR

650 mV

P-P

input range

870 mV

P-P

input range

Extended

Control

Mode

Pin 3 can be either high or low in the non-extended control

mode. Pin 14 must not be left floating to select this mode.

See Section 1.2 for more information.

Pin 4 can be high or low or can be left floating in the

non-extended control mode. In the non-extended control

mode, pin 4 high or low defines the edge at which the output

data transitions. See Section 2.4.3 for more information. If

this pin is floating, the output clock (DCLK) is a DDR (Double

Data Rate) clock (see Section 1.1.5.3) and the output edge

synchronization is irrelevant since data is clocked out on

both DCLK edges.

TABLE 9. Extended Control Mode Operation (Pin 14

Floating)

Function

SCLK (Serial Clock)

SDATA (Serial Data)

127

SCS (Serial Interface Chip Select)

2.10 COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power

supply rails. For device reliability, no input should go more

than 150 mV below the ground pins or 150 mV above the

supply pins. Exceeding these limits on even a transient basis

may not only cause faulty or erratic operation, but may

impair device reliability. It is not uncommon for high speed

digital circuits to exhibit undershoot that goes more than a

volt below ground. Controlling the impedance of high speed

lines and terminating these lines in their characteristic im-

pedance should control overshoot.

Care should be taken not to overdrive the inputs of the

ADC083000. Such practice may lead to conversion inaccu-

racies and even to device damage.

Incorrect analog input common mode voltage in the d.c.

coupled mode. As discussed in section 1.1.4 and 2.2, the

Input common mode voltage must remain within 50 mV of

the V

CMO output , which has a variability with temperature

that must also be tracked. Distortion performance will be

degraded if the input common mode voltage is more than 50

mV from V

CMO .

Using an inadequate amplifier to drive the analog input.

Use care when choosing a high frequency amplifier to drive

the ADC083000 as many high speed amplifiers will have

higher distortion than will the ADC083000, resulting in over-

all system performance degradation.

Driving the V

BG pin to change the reference voltage. As

mentioned in Section 2.1, the reference voltage is intended

to be fixed to provide one of two different full-scale values

(650 mV

P-P and 870 mVP-P). Over driving this pin will not

change the full scale value, but can be used to change the

LVDS common mode voltage from 0.8V to 1.2V by tying the

BG pin to VA.

Driving the clock input with an excessively high level

signal. The ADC input clock level should not exceed the

level described in the Operating Ratings Table or the input

offset could change.

Inadequate input clock levels. As described in Section 2.3,

insufficient input clock levels can result in poor performance.

Excessive input clock levels could result in the introduction

of an input offset.

Using a clock source with excessive jitter, using an

excessively long input clock signal trace, or having

other signals coupled to the input clock signal trace.

This will cause the sampling interval to vary, causing exces-

sive output noise and a reduction in SNR performance.

Failure to provide adequate heat removal. As described in

Section 2.6.2, it is important to provide adequate heat re-

moval to ensure device reliability. This can either be done

with adequate air flow or the use of a simple heat sink built

into the board. The backside pad should be grounded for

best performance.

ADC083000 bảng dữ liệu(PDF) 32 Page - National Semiconductor (TI)

ADC083000 bảng dữ liệu(HTML) 32 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

bảng dữ liệu tải về

Link URL