AP65352

Document number: DS38482 Rev. 2 - 3

10 of 15

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December 2017

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AP65352

Application Information (continued)

Soft-Start

The soft-start time of the AP65352 is programmable by selecting different CSS value. When the EN pin becomes high, the CSS is charged by a 6μA

current source, generating a ramp signal fed into non-inverting input of the error comparator. Reference voltage VREF or the internal soft-start

voltage SS (whichever is smaller), dominates the behavior of the non-inverting inputs of the error amplifier. Accordingly, the output voltage will

follow the SS signal and ramp up smoothly to its target level. The capacitor value required for a given soft-start ramp time can be expressed as:

SS

FB

SS

C

SS

t

I

V





Where CSS is the required capacitor between SS pin and PGND, tSS is the desired soft-start time and VFB is the feedback voltage.

Over Current Protection (OCP)

Figure 4 shows the overcurrent protection (OCP) scheme of AP65352. In each switching cycle, the inductor current is sensed by monitoring the

low-side MOSFET in the OFF period. When the voltage between PGND pin and SW pin is smaller than the overcurrent trip level, the OCP will be

triggered and the controller keeps the OFF state. A new switching cycle will begin when the measured voltage is larger than limit voltage. The

internal counter is incremented when OCP is triggered. After 16 sequential cycles, the internal OCL (Overcurrent Logic) threshold is set to a lower

level, reducing the available output current. When a switching cycle occurs where the switch current is below the lower OCL threshold, the counter

is reset and OCL limit is returned to higher value.

Because the RDS(ON) of MOSFET increases with temperature, VLimit has xppm/

oC temperature coefficient to compensate this temperature

dependency of RDS(ON).

OC

COMPARATOR

-266mV

Q1

Q2

S

Q

R

Figure 4 Overcurrent Protection Scheme

Undervoltage Lockout

The AP65352 provides an undervoltage lockout circuit to prevent it from undefined status during startup. The UVLO circuit shuts down the device

when VIN drops below 3.45V. The UVLO circuit has 320mV hysteresis, which means the device starts up again when VREG rises to 3.75V (non-

latch).

Thermal shutdown

If the junction temperature of the device reaches the thermal shutdown limit of +160°C, the AP65352 shuts itself off, and both HMOS and LMOS

will be turned off. The output is discharged with the internal transistor. When the junction cools to the required level (+130°C nominal), the device

initiates soft-start as during a normal power-up cycle.

Setting the Output Voltage

The output voltage can be adjusted from 1.000 to 5V using an external resistor divider. Table 1 shows a list of resistor selection for common

output voltages. Resistor R1 is selected based on a design tradeoff between efficiency and output voltage accuracy. For high values of R1 there is

less current consumption in the feedback network. However the tradeoff is output voltage accuracy due to the bias current in the error amplifier.

R1 can be determined by the following equation:



















1

0.765

OUT

V

2

R

1

R