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TDA7808 bảng dữ liệu(PDF) 28 Page - STMicroelectronics

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TDA7808 bảng dữ liệu(HTML) 28 Page - STMicroelectronics

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I2C bus interface
TDA7808
28/39
DS12230 Rev 4
9.7
I2C bus timings
This paragraph describes more in detail the I2C bus protocol used and its timings. Figure 32
and Table 10 include the timings that need to be respected in order to correctly write into/
read from the I2C registers.
Figure 32. I2C bus interface timing
1
0
30K < R < 38K
1
1
R < 15K
Table 9. Address threshold (continued)
ADD2
ADD1
Rload
Table 10. I2C bus interface timing
Symbol
Parameter
Min
Max
Unit
Fscl
SCL (clock line) frequency
-
400
kHz
Tscl
SCL period
2500
-
ns
Tsclh
SCL high time
0.6
-
μs
Tscll
SCL low time
1.3
-
μs
Tsstart
Setup time for start condition
0.6
-
μs
Thstart
Hold time for start condition
0.6
-
μs
Tsstop
Setup time for stop condition
0.6
-
μs
Tbuf
Bus free time between a stop and a start condition
1.3
-
μs
Tssda
Setup time for data line
100
-
ns
Thsda
Hold time for data line
0(1)
1. Device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined
region of the falling edge of SCL.
-ns
Tf
Fall time for SCL and SDA
-
300
ns



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