L9396 datasheet(84/109 Pages) STMICROELECTRONICS

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System functional safety implementations

L9396

84/109

DS12539 Rev 6

Figure 23. WD2 diagram

7.4.3

Watchdog Timer Disable Input (WDTDIS)

When controlled to a voltage higher than VIH_WDTDIS, this pin is used to disable the WD2

timer. It implements a passive pulldown to ensure the voltage level would not interrupt the

WD control in case of open connection. The state of this pin can be read by SPI because it

is acquired by an internal A2D converter. When WDTDIS pin is asserted, the watchdog

timer is disabled, the timer is reset to its starting value and no faults are generated. When

the watchdog timer is disabled, WD_2_RESET_FLAG bit is set to '0'.

-40°C ≤ Tj ≤ 175°C; 3 V ≤ VCC ≤ 5.5 V, unless otherwise specified.

Table 54. WD2 characteristics

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

FWDvalid WD2 Frequency valid range

ADV_CONFIG[14,13] = '00'

-750

ADV_CONFIG[14,13] = '01'

1500

ADV_CONFIG[14,13] = '10'

-750

ADV_CONFIG[14,13] = '11'

1500

Toff

WD2 timeout reset time

ADV_CONFIG[14] = '0'

16.5

ADV_CONFIG[14] = '1'

TRH

RESET re-engagement time

between two consecutive

assertion events

200

TWAIT

WD2 quiescent time at

power-up

200

RESET

Note: In case that PRN frequency is higher than 1 kHz WDT counter is not cleared.

PRN

RESET

tOFF

Toff

TRL

Toff

Pulse

Width

Counter

WDT

Counter

1ms (=1kHz)

GADG2501171008PS

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