L3751 datasheet(17/41 Pages) STMICROELECTRONICS

17 / 41 page

The VCC regulator provides the gate current for direct low-side and floating high-side driving, through the

bootstrap capacitor charge refresh. Make sure to select external MOSFETs in order that the total driving current

consumption is smaller than VCC regulator minimum output current capability at the programmed switching

frequency:

IDRV= QG HS+QG LS ∙fsw≤IVCC MIN=40mA

(4)

6.6

Light load operation

The device always implements diode emulation, so-called “DEM”, during soft-start to support pre-charged output

capacitor at device startup.

The state of the SYNCIN pin at power-up determines the light load operation: low logic level selects DEM, high

logic level or detected synchronization clock signal enables the forced PWM mode, so-called “FPWM”. In detail,

the DEM to FPWM transition is implemented smoothly ramping the zero current detecting threshold (ZCD) from 0

V to 200 mV in 1000 clock cycles starting from the first PWM pulse from the loop.

Figure 13. DEM vs. FPWM management in light load condition

The DEM mode operates in DCM and pulse skipping at light load, maximizing the efficiency in these application

conditions minimizing the conversion losses with controlled output voltage ripple.

The forced PWM (FPWM) over the load range makes the switching frequency constant and minimizes the output

voltage ripple, suggested for low noise application like sensors or analog circuitry supply.

L3751

Light load operation

DS13841 - Rev 1

page 17/41

L3751 bảng dữ liệu(PDF) 17 Page - STMicroelectronics