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AIS1200PS bảng dữ liệu(PDF) 6 Page - STMicroelectronics |
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AIS1200PS bảng dữ liệu(HTML) 6 Page - STMicroelectronics |
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6 / 21 page ![]() Block diagram and pin description AIS1200PS 6/21 DocID024648 Rev 4 Table 2. Pin description Pin# Name Function 1 - LV(1) 1. LV (low voltage) pin: 4.5 V max absolute rating. VREG Voltage regulator output. A ceramic capacitor of 1.0 F ± 40% must be connected to this pin, which should not be used to power up other devices. 2 - LV CLK SPI interface - connect to GND. 3 - LV SDI SPI interface - connect to GND. 4 - LV SDO SPI interface - driven to “0” by the device. 5 - LV DR Data Ready - driven to “0” by the device. 6 - LV CS SPI chip select, connect to GND. 7 - LV AT1 Analog port 1 - driven to “0” by the device. 8 - LV AT2 Analog port 2 - driven to “0” by the device. 9 - LV SH Connect to GND. 10 - LV AT3 Analog port 3 - driven to “0” by the device. 11 - LV AT4 Analog port 4 - driven to “0” by the device. 12 - LV Reserved Leave unconnected. 13 - LV Reserved Connect to GND. 14 - HV(2) 2. HV (high voltage) pin: 20 V max absolute rating. RTN Bus low side. 15 - HV BUSIN Bus high side. 16 - HV HCAP An autarky ceramic capacitor of 0.047 F ± 50% must be connected to this pin. |
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