VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-39-
02H-
04H
sram address register
The data object addressed is in unit of 64 bits.
The maximum allowable SRAM size is 1MB. For
SRAM direct access, the CPU has to (1) set
SRAMADDR & SRAMDATA, (2) issue read/write
command by SRAMCMD, and (3) check
command status by SRAMSTS.
SRAMADDR
[16:0]
R/W
05H-
0CH
sram data register
SRAMDATA
[63:0]
R/W
0DH
sram command register
2’ b00 : nop
2’ b01 : read
2’ b10 : write
SRAMCMD
[1:0]
R/W
0EH
sram status register
2’ b01 : read/write command done
2’ b10 : busy (read/write in progress)
2’ b00 : idle
SRAMSTS
[1:0]
0
R/O
0FH
Interrupt Mode
INTRQ_MODE == 0 => High Active
INTRQ_MODE == 1 => Low Active (default)
INTRQ_MODE
[0]
1
R/W
10H
Write packet command
3’ b100 : end of frame with the remaining data
size = 2 byte
3’ b101 : end of frame with the remaining data
size = 1 byte
3’ b000 : idle
3’ b001 : start of frame for the next write
3’ b010 : middle of frame for the next write
3’ b011 : abort the unfinished packet write
CPU should write this command register before
repeatedly writing 8 bit packet data to CPU
Interface Control via the 8-bit IDE bus.
The cpu interface with external is 8bit bus.
However the interface between cpuif and cpuioctl
is 16bit data bus. The WR_PKT_CMD will be
passed to cpuioctl so that it will know all the 16bit
are valid or only 8 bit are valid data. For cpu to
send packet, the steps are as follows:
write WR_PKT_CMD = 3'b001 to notify start of
frame, then write first 2 byte data via IDE.
write WR_PKT_CMD = 3'b010 to notify middle of
frame, then write even number of data via IDE.
Leave last two or one byte data.
write WR_PKT_CMD = 3'b100 or 3'b101 to notify
end of frame with remaining data 2 byte or 1 byte.
If it is 2 byte, write the last two byte data via IDE.
If it is 1 byte, write the last one byte data first, and
then write another byte for dummy padding.
WR_PKT_CMD
[2:0]
W/O
R/W
11H
Packet Abort
Writing 1’ b1 to this register will drop an incoming
packet ready to be read by CPU. Reading this
register will clear this register as 1’ b0.
PKT_ABORT
[0]
R/W
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