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74HC/HCT283 bảng dữ liệu(PDF) 2 Page - NXP Semiconductors |
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74HC/HCT283 bảng dữ liệu(HTML) 2 Page - NXP Semiconductors |
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2 / 8 page ![]() December 1990 2 Philips Semiconductors Product specification 4-bit binary full adder with fast carry 74HC/HCT283 FEATURES • High-speed 4-bit binary addition • Cascadable in 4-bit increments • Fast internal look-ahead carry • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT283 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT283 add two 4-bit binary words (An plus Bn) plus the incoming carry. The binary sum appears on the sum outputs ( ∑1 to ∑4) and the out-going carry (COUT) according to the equation: CIN + (A1 + B1) + 2(A2 + B2) ++4(A3 + B3) + 8(A4 + B4)= = ∑1 + 2∑2 + 4∑3 + 8∑4 + 16COUT Where ( +) = plus. Due to the symmetry of the binary add function, the “283” can be used with either all active HIGH operands (positive logic) or all active LOW operands (negative logic); see function table. In case of all active LOW operands the results ∑1 to ∑4 and COUT should be interpreted also as active LOW. With active HIGH inputs, CIN must be held LOW when no “carry in” is intended. Interchanging inputs of equal weight does not affect the operation, thus CIN, A1, B1 can be assigned arbitrarily to pins 5, 6, 7, etc. See the “583” for the BCD version. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay CL = 15 pF; VCC =5 V CIN to ∑1 16 15 ns CIN to ∑2 18 21 ns CIN to ∑3 20 23 ns CIN to ∑4 23 27 ns An or Bn to ∑n 21 25 ns CIN to COUT 20 23 ns An or Bn to COUT 20 24 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 88 92 pF |
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