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HT95C40P bảng dữ liệu(PDF) 16 Page - Holtek Semiconductor Inc |
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HT95C40P bảng dữ liệu(HTML) 16 Page - Holtek Semiconductor Inc |
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16 / 51 page  HT95CXXX Rev. 1.50 16 May 26, 2005 Note: 1. If the dialer status is on-hook and hold-line, the falling edge transition onto HDI pin will not generate the dialer I/O interrupt. 2. The dialer I/O interrupt will be disabled when the operation mode is in Idle mode. During the execution of an interrupt subroutine, other in- terrupt acknowledge signals are held until the RETI in- struction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter- rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source Priority Vector External interrupt 1 04H Timer/Event Counter 0 interrupt 2 08H Timer/Event Counter 1 interrupt 3 0CH Peripheral interrupt 4 10H Real time clock interrupt 5 14H Dialer I/O interrupt 6 18H Priority of the Interrupt EMI, EEI, ET0I, ET1I, EPERI, ERTCI and EDRI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (EIF, T0F, T1F, PERF, RTCF, DRF) are set by hardware or soft- ware, they will remain in the INTC0 or INTC1 registers until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use the ²CALL subroutine² within the interrupt subroutine. Inter- rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be dam- aged once the ²CALL² operates in the interrupt subrou- tine. Oscillator Configuration There are two oscillator circuits in the controller, the ex- ternal 32768Hz crystal oscillator and internal WDT OSC. The 32768Hz crystal oscillator and frequency-up con- version circuit (32768Hz to 3.58MHz) are designed for dual system clock source. It is necessary for frequency conversion circuit to add external RC components to make up the low pass filter that stabilize the output fre- quency 3.58MHz (see the oscillator circuit). The WDT OSC is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the Idle mode (the system clock is stopped), the WDT OSC still works within a period of 78 ms normally. When the WDT is disabled or the WDT source is not this RC oscillator, the WDT OSC will be disabled. Watchdog Timer - WDT The WDT clock source is implemented by a WDT OSC or external 32768Hz or an instruction clock (system clock divided by 4), determined by the mask option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with un- predictable results. The Watchdog Timer can be dis- abled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no opera- tion. If the device operates in a noisy environment, using the on-chip WDT OSC or 32768Hz crystal oscillator is strongly recommended. When the WDT clock source is selected, it will be first di- vided by 512 (9-stage) to get the nominal time-out pe- riod. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 can give different time-out periods. The WDT OSC period is 78 ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC always works for any operation mode. If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the Sleep mode or Idle mode. In these two modes, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. If the WDT clock source is the 32768Hz, the WDT also operates in the same manner except in the Idle mode. X 1 X 2 X C 1 5 k W 3 n F 5 0 n F System Oscillator Circuit S y s t e m C l o c k / 4 9 - b i t C o u n t e r W D T P r e s c a l e r 7 - b i t C o u n t e r 8 - t o - 1 M U X W D T T i m e - o u t W S 0 ~ W S 2 M a s k O p t i o n S e l e c t W D T O S C 3 2 7 6 8 H z Watchdog Timer |
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