HT45R06 datasheet(13/41 Pages) HOLTEK

13 / 41 page

HT45R06

Rev. 1.00

May 24, 2005

To guarantee that the system oscillator is started and

stabilized, the CSST (System Start-up Timer) provides

an extra delay of 2.5ms when the system resets

(power-up, WDT time-out or RES reset) or awakes from

the HALT state.

When a system reset occurs, the CSST delay is added

during the reset period. Any wake-up from HALT will en-

able the CSST delay.

An extra option load time delay is added during system

reset (power-up, WDT time-out at normal mode or RES

reset).

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter

Off

Input/Output Ports

Input mode

Points to the top of the stack

The registers state are summarized in the following table.

Reset

(Power On)

WDT time-out

(Normal Operation)

RES Reset

(Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

-xxx xxxx

-uuu uuuu

ACC

xxxx xxxx

uuuu uuuu

Program

Counter

000H

TBLP

xxxx xxxx

uuuu uuuu

TBLH

--xx xxxx

--uu uuuu

OSCC

---- ---1

STATUS

--00 xxxx

--1u uuuu

--uu uuuu

--01 uuuu

--11 uuuu

INTC

-000 0000

-uuu uuuu

TMR

xxxx xxxx

uuuu uuuu

TMRC

00-0 1000

uu-u uuuu

1111 1111

uuuu uuuu

PAC

1111 1111

uuuu uuuu

---- 1111

---- uuuu

PBC

---- 1111

---- uuuu

---- ---1

---- ---u

PDC

---- ---1

---- ---u

ADR

xxxx xxxx

uuuu uuuu

ADCR

0100 0000

uuuu uuuu

ACSR

1--- --00

u--- --uu

Note:

²*² means ²warm reset²

²u² means ²unchanged²

²x² means ²unknown²

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