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PIC16F87-I/ML bảng dữ liệu(PDF) 209 Page - Microchip Technology

tên linh kiện PIC16F87-I/ML
Giải thích chi tiết về linh kiện  18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology
PDF  214 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F87-I/ML bảng dữ liệu(HTML) 209 Page - Microchip Technology

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 2003 Microchip Technology Inc.
Preliminary
DS30487B-page 207
PIC16F87/88
TXSTA Register ................................................................. 15
BRGH Bit ................................................................... 97
CSRC Bit .................................................................... 97
SYNC Bit .................................................................... 97
TRMT Bit .................................................................... 97
TX9 Bit ....................................................................... 97
TX9D Bit ..................................................................... 97
TXEN Bit .................................................................... 97
U
USART ............................................................................... 97
Address Detect Enable (ADDEN Bit) ......................... 98
Asynchronous Mode ................................................ 102
Asynchronous Receive (9-bit Mode) ........................ 106
Asynchronous Receive with Address Detect.
See Asynchronous Receive (9-bit Mode).
Asynchronous Receiver ........................................... 104
Asynchronous Reception ......................................... 105
Asynchronous Transmitter ....................................... 102
Baud Rate Generator (BRG) ...................................... 99
Baud Rate Formula ............................................ 99
Baud Rates, Asynchronous Mode
(BRGH = 0) .............................................. 100
Baud Rates, Asynchronous Mode
(BRGH = 1) .............................................. 100
High Baud Rate Select (BRGH Bit) .................... 97
INTRC Baud Rates, Asynchronous Mode
(BRGH = 0) .............................................. 101
INTRC Baud Rates, Asynchronous Mode
(BRGH = 1) .............................................. 101
INTRC Operation ............................................... 99
Low-power Mode Operation ............................... 99
Sampling ............................................................ 99
Clock Source Select (CSRC Bit) ................................ 97
Continuous Receive Enable (CREN Bit) .................... 98
Framing Error (FERR Bit) .......................................... 98
Mode Select (SYNC Bit) ............................................ 97
Receive Data, 9th bit (RX9D Bit) ............................... 98
Receive Enable, 9-bit (RX9 Bit) ................................. 98
Serial Port Enable (SPEN Bit) .............................. 97, 98
Single Receive Enable (SREN Bit) ............................ 98
Synchronous Master Mode ...................................... 108
Synchronous Master Reception ............................... 110
Synchronous Master Transmission .......................... 108
Synchronous Slave Mode ........................................ 111
Synchronous Slave Reception ................................. 112
Synchronous Slave Transmit ................................... 111
Transmit Data, 9th Bit (TX9D) .................................... 97
Transmit Enable (TXEN Bit) ....................................... 97
Transmit Enable, Nine-bit (TX9 Bit) ........................... 97
Transmit Shift Register Status (TRMT Bit) ................. 97
USART Synchronous Receive Requirements .................. 187
V
VDD Pin ................................................................................ 9
Voltage Reference Specifications .................................... 175
VSS Pin ................................................................................ 9
W
Wake-up from SLEEP ...............................................129, 146
Interrupts ................................................................. 135
MCLR Reset ............................................................ 135
WDT Reset .............................................................. 135
Wake-up Using Interrupts ................................................ 146
Watchdog Timer (WDT) ............................................129, 141
Associated Registers ............................................... 142
WDT Reset, Normal Operation .........................132, 135
WDT Reset, SLEEP ..........................................132, 135
WCOL ................................................................................ 89
WDTCON Register ............................................................ 16
Write Collision Detect Bit, WCOL ...................................... 89
WWW, On-Line Support ...................................................... 4



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