CC2430-RTR1-F64Z datasheet(127/234 Pages) TI

127 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 127 of 232

13.7 ADC

13.7.1 ADC Introduction

The ADC supports up to 14-bit analog-to-

digital conversion. The ADC includes an

analog multiplexer with up to eight

individually

configurable

channels,

reference

voltage

generator

and

conversion results written to memory

through DMA. Several modes of operation

are available.

The main features of the ADC are as

follows:

•

Selectable decimation rates which

also sets the resolution (8 to 13 bits).

•

Eight individual input channels, single-

ended or differential

•

Reference

voltage

selectable

internal,

external

single

ended,

external differential or AVDD_SOC.

•

Interrupt request generation

•

DMA triggers at end of conversions

•

Temperature sensor input

•

Battery measurement capability

input

mux

Sigma-delta

modulator

Decimation

filter

Clock generation and

control

AIN0

AIN7

ref

mux

input

mux

VDD/3

TMP_SENSOR

Int 1.25V

AIN7

AVDD

AIN6-AIN7

Figure 26: ADC block diagram.

13.7.2 ADC Operation

This section describes the general setup

and operation of the ADC and describes

the usage of the ADC control and status

registers accessed by the CPU.

13.7.2.1 ADC Core

The ADC includes an ADC capable of

converting an analog input into a digital

representation

with

bits

resolution. The ADC uses a selectable

positive reference voltage.

13.7.2.2 ADC Inputs

The signals on the P0 port pins can be

used as ADC inputs. In the following these

port pin will be referred to as the AIN0-

AIN7 pins. The input pins AIN0-AIN7 are

connected to the ADC. The ADC can be

set

automatically

perform

sequence of conversions and optionally

perform an extra conversion from any

channel when the sequence is completed.

It is possible to configure the inputs as

single-ended or differential inputs. In the

case where differential inputs are selected,

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