CC2430-RTR1-F64Z datasheet(91/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 91 of 232

MOV DMAARM, #0x03

; arm DMA channel 0 and 1

MOV DMAARM, #0x81

; disarm DMA channel 0,

; channel 1 is still armed

Figure 19: DMA arm/disarm example

13.2.5 DMA Interrupts

Each DMA channel can be configured to

generate an interrupt to the CPU upon

completing

DMA

transfer.

This

accomplished with the IRQMASK bit in the

channel configuration. The corresponding

interrupt flag in the DMAIRQ SFR register will

be set when the interrupt is generated.

Regardless of the IRQMASK bit in the channel

configuration, the interrupt flag will be set upon

DMA channel complete. Thus software should

always check (and clear) this register when

rearming a channel with a changed IRQMASK

setting. Failure to do so could generate an

interrupt based on the stored interrupt flag.

13.2.6 DMA Configuration Data Structure

For each DMA channel, the DMA configuration

data structure consists of eight bytes. The

configuration data structure is described in

Table 38.

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