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MPFS250T bảng dữ liệu(PDF) 43 Page - Microchip Technology

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MPFS250T bảng dữ liệu(HTML) 43 Page - Microchip Technology

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Conditions
Units
Max
Typ
Min
Symbol
Parameter
VIN = 0, f = 1.0 M-
Hz
pF
10
Ci
Input capaci-
tance
pF
Cb
Capacitive load
for each bus line
PCLK
1
TI2CL
Low period of S-
CL clock
cycles
PCLK
1
TI2CH
High period of
SCL clock
cycles
PCLK
1
Tsu(start)
Setup time for a
repeated START
condition
cycles
PCLK
1
Th(start)
Hold time for a
repeated START
cycles
condition (after
this period, the
first clock pulse
is generated)
PCLK
1
Tsu(data)
Data setup time
cycles
PCLK
1
Th(data)
Data input hold
time
cycles
PCLK
1
Tod(data)
Data output de-
lay time
cycles
PCLK
1
Tsu(stop)
Setup time for
STOP condition
cycles
PCLK
1
Tbuf
Bus free time
between a STOP
cycles
and START condi-
tion
6.1.13
Watchdog Timer
The following table describes the watchdog timer (WDT).
Table 54 • Watchdog timer
Units
Max
Min
Symbol
Parameter
MHz
250
FWDTCLK
Watchdog timer input
clock frequency
6.1.14
Timers
The following table describes the timers.
39
Microsemi Proprietary and Confidential. DS0147 Revision 1.0
AC Switching Characteristics



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