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DM9101F bảng dữ liệu(PDF) 33 Page - List of Unclassifed Manufacturers

tên linh kiện DM9101F
Giải thích chi tiết về linh kiện  10/100Mbps Ethernet Physical Layer Single Chip Transceiver
PDF  43 Pages
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nhà sản xuất  ETC1 [List of Unclassifed Manufacturers]
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DM9101F bảng dữ liệu(HTML) 33 Page - List of Unclassifed Manufacturers

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DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Final
33
Version: DM9101-DS-F03
July 22, 1999
MII-100Base-TX Transmit Timing Diagram
TX_CLK
tTX
h
t2
tTX
S
t1
tTX
pd
tTX
r/f
TXD [0:3],
TX_EN, TX_ER
CRS
100TX+/-
MII-100Base-TX Transmit Timing Parameters
(Half Duplex)
Symbol
Parameter
Min.
Typ1.
Max.
Unit
Conditions
tTX
s
TXD[0:3], TX_EN, TX_ER Setup
To TX_CLK High
11
-
-
ns
tTX
h
TXD[0:3], TX_EN, TX_ER Hold
From TX_CLK High
0-
-
ns
t1
TX_EN Sampled To CRS
Asserted
-4
-
BT
t2
TX_EN Sampled To CRS De-
asserted
-4
-
BT
tTX
pd
TX_EN Sampled To TPO Out (Tx
Latency)
-8
-
BT
tTX
r/f
100TX Driver Rise/Fall Time
3
4
5
ns
90% To 10%, Into
100ohm Differential
1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing.
MII-100Base-TX Receive Timing Diagram
RX_CLK
t2
t1
tTX
pd
RXD [0:3],
RX_DV, RX_ER
CRS
RXI+/-
tRX
S
tRX
h
t4
t3
COL
t5



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