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FXLS8964AF bảng dữ liệu(PDF) 20 Page - NXP Semiconductors

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FXLS8964AF bảng dữ liệu(HTML) 20 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8964AF
3-Axis Low-g Accelerometer
aaa-040844
tHCS
tSCLKL
tSCLKH
tSCLK
tSCS
tSET
tHOLD
tWCS
SPI_CS_B
SCLK
SPI_MOSI
SPI_MISO
tDDLY
tHZ
High-Impedance
High-Impedance
Figure 12. SPI timing diagram (4-wire mode)
13.6 SPI timing specifications (software enabled 3-wire mode)
Table 14 and Figure 13 specify and illustrate the minimum and maximum timing
parameter values for correct SPI interface functionality when FXLS8964AF is operated
in 3-wire (software enabled) SPI mode. FXLS8964AF only supports SPI mode '00',
corresponding to CPOL = 0, and CPHA = 0. In this mode, the active state of the
clock is high and the idle state is low. Data is latched on the rising edge of the clock
and propagated on the falling edge. All timing specifications shown in Table 14 were
determined under the following conditions: 10 pF capacitor and 1 kΩ pull-up resistor
present on all SPI signals, 105 °C, 1.8 V.
Note: When FXLS8964AF is operated in 3-wire SPI mode - by setting
SENS_CONFIG1[SPI_M] = 1 - the SA0/SPI_MISO pin is always placed in a high
impedance (high-z) state, with the SPI_MISO pin output driver disabled (tri-stated).
Specifications
Label
Description
Min.
Max.
Unit
fSCLK
SCLK frequency
0
4
MHz
tSCLK
SCLK Period
250
—
ns
tSCLKH
SCLK high time
100
—
ns
tSCLKL
SCLK low time
100
—
ns
tSCS
Setup time for SPI_CS_B signal
125
—
ns
tHCS
Hold time for SPI_CS_B signal
240
—
ns
tHZ
Hold time for SPI_DATA signal transition
back to high-impedance state
—
25
ns
tWCS
Inactive time for SPI_CS_B signal
600
—
ns
tSET
Data setup time for SPI_DATA signal
10
—
ns
tHOLD
Data hold time for SPI_DATA signal
10
—
ns
tDDLY
Data setup time for SPI_DATA signal (output
phase)
—
50
ns
Table 14.  Secondary timing values
FXLS8964AF
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 3.4 — 7 December 2021
20 / 98



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