TP5322

Rev. 3

September 14, 2004

1

Initial Release

P-Channel Enhancement-Mode

Vertical DMOS FET

Features

Application

Absolute Maximum Ratings

Drain-to-Source Voltage

Drain-to-Gate Voltage

Gate-to-Source Voltage

±20V

Operating and Storage Temperature

-55°C to +150°C

Soldering Temperature****

300°C

****Distance of 1.6mm from case for 10 seconds.

General Description

These

low

threshold

enhancement-mode

(normally-off)

transistors utilize an advanced vertical DMOS structure and

Supertex's well-proven silicon-gate manufacturing process. This

combination produces devices with the power handling

capabilities of bipolar transistors and with the high input

impedance and positive temperature coefficient inherent in MOS

devices. Characteristic of all MOS structures, these devices are

free from thermal runaway and thermally-induced secondary

breakdown.

Supertex's vertical DMOS FETs are ideally suited to a wide

range of switching and amplifying applications where very low

threshold

voltage,

high

breakdown

voltage,

high

input

impedance, low input capacitance, and fast switching speeds are

desired.

Package Options

Ordering Information

Order Number / Package

TO-243AA**

TO-236AB***

(max)

(max)

(min)

TP5322N8

TP5322K1

-220V

12

Ω

-2.4V

-0.7A

TP5322N8-G*

TP5322K1-G*

-220V

12

Ω

-2.4V

-0.7A

**Same as SOT-89. Product supplied on 2000 piece carrier tape reels.

***Same as SOT-23. Products supplied on 3000 piece carrier tape reels.

TP5322

A042005

* "Green" Certified Package

D

S

D

G

D

S

G

TO-236AB

(SOT-23)*

TO-243AA

(SOT-89)*

Product Marking for SOT-89

TP3C

✶

Where

✶=2-week alpha date code

Product Marking for SOT-23

P3C

✶

Where

✶=2-week alpha date code