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ATLS500MA103 bảng dữ liệu(PDF) 3 Page - Analog Technologies, Inc. |
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ATLS500MA103 bảng dữ liệu(HTML) 3 Page - Analog Technologies, Inc. |
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3 / 11 page ![]() 1161 Ringwood Ct, #110, San Jose, CA 95131, U. S. A. Tel.: (408) 748-9100, Fax: (408) 770-9187 www.analogtechnologies.com Copyrights 2000-2022, Analog Technologies, Inc. All Rights Reserved. Updated on 1/18/2022 Email: staff@analogti.com/sales@analogti.com 3 Analog Technologies ATLS500MA106 Low Noise Constant Current Laser Controller APPLICATIONS Figure 4.1 shows a typical application circuit. W1 and W2 set the output current limit and output current respectively. Resistor R1 and capacitor C1 form a low pass filter, to lower the noise from the voltage reference. Laser diode D1 is connected between LDA and PGND. It is worth mentioning that the power supply return terminal should be connected to the pin 11 PGND and the cathode of the laser diode should be connected to the pin 10 LDC. These 2 nodes should not be connected together externally and they are connected together internally already by the controller. Power Supply 5V Power Supply 0V To ADC To ADC 1 2 D1 Laser Diode 1 2 D2 LED Loop Good Indication 1 2 S1 SPST Shut Down SBDN 1 GND 2 2.5VR 3 LIMS 4 LIS 5 LIO 6 VPS 12 PGND 11 LDC 10 LDA 9 TMPO 8 LPGD 7 ATLS250MA106 3 W1 20K 3 W2 20K 1 2 C1 100uF 6.3V Current Set (Clock-wise) 1206 Current Limit Set (Clock-Wise) MLC Capacitor 1 2 R1 100K Figure 4.1. Typical Stand-alone CW Operation Schematic for ATLS500MA106 Power Supply 5V Power Supply 0V To ADC To ADC 1 2 D1 Laser Diode 1 2 D2 LED Loop Good Indication 1 2 S1 SPST Shut Down SBDN 1 GND 2 2.5VR 3 LIMS 4 LIS 5 LIO 6 VPS 12 PGND 11 LDC 10 LDA 9 TMPO 8 LPGD 7 ATLS500MATF-S 3 W1 20K 3 W2 20K 1 2 R1 100K 1206 MLC Capacitor Current Limit Set (Clock-Wise) Current Set (Clock-wise) 1 2 R2 100K AC Modulation Signal 1 2 1uF to 100uF C2 1 2 100uF 6.3V C1 Figure 4.2. Typical AC Modulation with DC bias Schematic for ATLS500MA106 ATLS500MATF ATLS250MA106 ATLS500MA106 ATLS500MA106 |
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