HV461

13

37

CL-

Current limit amplifier inverting input.

38

CLCOMP

Current limit compensation. An RC network connected between this pin and CL- establishes current limit

reaction time and stability.

39

DIFFAMP+

Differential amplifier non-inverting input.

The differential amplifier sets gain, establishing output

40

DIFFAMP-

Differential amplifier inverting input.

amplitude and DC offset in conjunction with AMPx and OFFx.

41

DIFFAMPO

Differential amplifier output.

42

COMP2

Error amplifier compensation. An RC network connected between these pins establishes loop stability.

43

COMP1

COMP1 is the error amp inverting input. COMP2 is the error amp output.

44

SINEREF

Ω. An external 33nF

capacitor from this pin to ground should be employed to remove high frequency synthesizer ripple. Synthesizer

ripple is at a frequency of 2

45

AGND

Analog ground. Connect to AGND and DGND close to the IC.

46

VDCL

Voltage applied to this pin sets the min/max duty cycle limits. If the PWM controller hits these limits, clipping of

47

DCREF1

In conjunction with the OFFx control inputs, voltages applied to these inputs set the output DC offset.

48

DCREF2

Output offset is the selected DCREFx voltage multiplied by gain. See also OFF0 & OFF1 (pins 17 & 18)

10/3/03

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