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VSC8021 bảng dữ liệu(PDF) 9 Page - Vitesse Semiconductor Corporation |
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VSC8021 bảng dữ liệu(HTML) 9 Page - Vitesse Semiconductor Corporation |
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9 / 17 page ![]() VITESSE SEMICONDUCTOR CORPORATION G52028-0, Rev 4.1 Page 9 05/25/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Data Sheet VSC8021/VSC8022 8-Bit MUX/DEMUX Chipset 2.5Gb/s SONET-Compatible Figure 5: SONET Frame Structure High-Speed Inputs In the past, the high-speed inputs, which are typically used for serial data and high-speed clock inputs with frequencies greater than 1GHz, were specified with absolute minimum and maximum voltage values. Since these inputs are intended for AC-coupled applications, they have been re-specified in terms of a voltage swing ( ∆V IN). High-speed clocks are intended for AC-coupled operation. In most situations high-speed serial data will have high transition density and contain no DC offsets, making them candidates for AC-coupling as well. How- ever, it is possible to employ DC-Pcoupling when the serial input data contains a DC component. The structure of the high-speed input circuit is shown in Figure 6. DC-coupled circuits may be used to oper- ate this input provided that the input swing is centered around the reference voltage. It is recommended that, in single-ended DC-coupling situations, the user provide an external reference which has better temperature and power supply rejection than the simple on-chip voltage divider. This external reference should have a nominal value of -3.5V and can be connected to the complementary input. This complication can be avoided in DC-cou- pled situations by using differential signals. Figure 6: High-Speed Input Circuit Structure 3 x 3 Bytes Transport Overhead STS-3 Envelope Capacity 125 µs STS-3 Frame 3 x 90 Bytes A1s and A2s: SONET Framing Sequence C1s: STS Frame ID DATA 3 A1s 9 Rows 3 A2s 3 C1s 3 x 48 Bytes Transport Overhead STS-48 Envelope Capacity 125 µs STS-48 Frame 48 x 90 Bytes DATA 48 A1s 9 Rows 48 A2s 48 C1s 50• Chip Boundary -3.5 V -3.5 V VCC = GND VEE = -5.2V 150 pF VTT VTT R • 1k• 150 pF Ω |
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