VSC8540XMVRT-HC datasheet(58/87 Pages) MICROCHIP

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VSC8540RT

DS60001603E-page 58

 2022 Microchip Technology Inc. and its subsidiaries

6.4.12

EXTENDED INTERRUPT STATUS

The following table shows the register settings for the extended interrupt status at address 29E2.

6.5

General Purpose Registers

Accessing the general purpose register space is similar to accessing the extended page registers. Set register 31 to

0x0010. This sets all 32 registers to the general purpose register space.

To restore main register page access, write 0x0000 to register 31. All general purpose register bits are super-sticky.

6.5.1

CLKOUT CONTROL

The CLKOUT control register configures the functionality of the CLKOUT output pin.

TABLE 6-47:

EXTENDED INTERRUPT STATUS, ADDRESS 29E2 (0X1D)

Bit

Name

Access

Description

Default

15:14

Reserved

Reserved.

Rx FIFO overflow/underflow interrupt status

Self-clearing bit.

1: Interrupt pending.

Tx FIFO overflow/underflow interrupt status

Self-clearing bit.

1: Interrupt pending.

11:4

Reserved

Reserved.

EEE link fail interrupt status

Self-clearing bit.

1: Interrupt pending.

EEE Rx TQ timer interrupt status

Self-clearing bit.

1: Interrupt pending.

EEE wait quiet/Rx TS timer interrupt status

Self-clearing bit.

1: Interrupt pending.

EEE wake error interrupt mask

Self-clearing bit.

1: Interrupt pending.

TABLE 6-48:

GENERAL PURPOSE REGISTERS SPACE

Address

Name

0G–12G

Reserved

13G

CLKOUT Control

14G

GPIO Control 2

15G–18G

Reserved

19G

Fast Link Register

20G–22G

Reserved

23G

Recovered Clock Control

24G

Reserved

25G

Enhanced LED Control

26G–30G

Reserved

TABLE 6-49:

CLKOUT CONTROL, ADDRESS 13G (0X0D)

Bit

Name

Access

Description

Default

CLKOUT enable

R/W

1: CLKOUT enabled.

0: CLKOUT disabled.

14:13

CLKOUT frequency select R/W

00: 25 MHz.

01: 50 MHz.

10: 125 MHz.

11: Reserved.

12:0

Reserved

Reserved.

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