AD7405BRIZ datasheet(14/20 Pages) AD

14 / 20 page

AD7405

Data Sheet

To reconstruct the original information, this output must be

digitally filtered and decimated. A sinc3 filter is recommended

because it is one order higher than that of the AD7405 modulator,

which is a second-order modulator. If a 256 decimation rate is

used, the resulting 16-bit word rate is 78.1 kSPS, assuming a

20 MHz external clock frequency. See the Digital Filter section

for more detailed information on the sinc filter implementation.

Figure 23 shows the transfer function of the AD7405 relative to

the 16-bit output.

Figure 23. Filtered and Decimated 16-Bit Transfer Function

DIFFERENTIAL INPUTS

The analog input to the modulator is a switched capacitor

design. The analog signal is converted into charge by highly

linear sampling capacitors. A simplified equivalent circuit

diagram of the analog input is shown in Figure 24. A signal

source driving the analog input must provide the charge onto

the sampling capacitors every half MCLKIN cycle and settle to the

required accuracy within the next half cycle.

Figure 24. Analog Input Equivalent Circuit

Because the AD7405 samples the differential voltage across its

analog inputs, an input circuit provides low common-mode

noise at each input attaining low noise performance.

LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)

INTERFACE

The AD7405 uses an LVDS interface for both the clock input

and the modulator output. The benefits of using LVDS in this

case helps to make the interface between the modulator and the

controller more robust and less susceptible to electromagnetic

interference (EMI) from the surroundings. LVDS also helps to

reduce the EMI emissions associated with high speed digital

signaling. LVDS signals are treated like transmission lines and

must be resistively terminated. The value of the differential

terminating resistor is typically 100 Ω. Place the terminating

resistor as close to the receiver as possible.

65535

58368

SPECIFIED RANGE

ANALOG INPUT

7168

–320mV

–250mV

+250mV

+320mV

φA

φB

300Ω

VIN–

φA

φB

300Ω

VIN+

1.9pF

φA

MCLKIN

Rev. A | Page 14 of 20

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