TDF8599BTH datasheet(23/54 Pages) NXP

23 / 54 page

NXP Semiconductors

TDF8599B

I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with

load diagnostics

TDF8599B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 23 August 2016

23 / 54

In non-I2C mode or when IB3[D7] = 0, the information on the MOD and ADS pins is

latched when one of the TDF8599B’s outputs starts switching.

STOP

START

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SCL

SDA

Mµp

SLAVE

(1)

(1) When SCL is HIGH, SDA changes to form the start or

stop condition.

Figure 22. I2C-bus start and stop conditions

SCL

SDA

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(2)

(1)

Mµp

SLAVE

(1) SDA is allowed to change.

(2) All data bits must be valid on the positive edges of SCL.

Figure 23. Data bits sent from Master microprocessor

(Mµp)

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LSB + 1

LSB

MSB - 1

MSB

MSB - 1

MSB

ACK

ACK(1)

ACK

STOP

WRITE DATA

WRITE

START

ADDRESS

SCL

SDA

Mµp

SLAVE

(1) To stop the transfer after the last acknowledge a stop condition must be generated.

Figure 24. I2C-bus write

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LSB + 1

LSB

MSB - 1

MSB

MSB - 1

MSB

ACK

ACK(1)

ACKNOWLEDGE

STOP

READ DATA

READ

START

ADDRESS

SCL

SDA

Mµp

SLAVE

(1) To stop the transfer, the last byte must not be acknowledged (SDA is HIGH) and a stop condition must be generated.

Figure 25. I2C-bus read

9.1 Instruction bytes

If R/W bit = 0, the TDF8599B expects three instruction bytes: IB1, IB2 and IB3. After a

power-on reset, all unspecified instruction bits must be set to zero.

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