TDF8599B datasheet(32/54 Pages) NXP

32 / 54 page

NXP Semiconductors

TDF8599B

I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with

load diagnostics

TDF8599B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 23 August 2016

32 / 54

Symbol Parameter

Conditions

Min

Typ Max

Unit

ηpo

output power efficiency

Po = 20 W

[1]

Rs(L) is the sum of the inductor series resistance from the low-pass LC filter in the application together with all resistance from PCB traces or wiring

between the output pin of the TDF8599B and the inductor to the measurement point. LC filter dimensioning is L = 10 μH, C = 1 μF for 4 Ω load and L = 5

μH, C = 2.2 μF for 2 Ω load.

[2]

Output power is measured indirectly based on RDSon measurement.

[3]

Total harmonic distortion is measured at the bandwidth of 22 Hz to 20 kHz, AES brick wall. The maximum limit is guaranteed but may not be 100 %

tested.

[4]

Vripple = Vripple(max) = 2 V (p-p); Rs = 0 Ω.

[5]

B = 22 Hz to 20 kHz, AES brick wall, Rs = 0 Ω.

[6]

B = 22 Hz to 20 kHz, AES brick wall, independent of Rs.

[7]

Vi = Vi(max) = 0.5 V RMS.

14 Application information

14.1 Output power estimation (Stereo mode)

The output power, just before clipping, can be estimated using Equation 5:

(5)

Where,

• VP = supply voltage (V)

• RL = load impedance (Ω)

• RDSon = drain-source on-state resistance (Ω)

• Rs = series resistance of the output inductor (Ω)

• tw(min) = minimum pulse width(s) depending on output current (s)

• fosc = oscillator frequency in Hz (typically 320 kHz)

The output power at 10 % THD can be estimated by:

Po(2) = 1.25 × Po(1)

where Po(1) = 0.5 % and Po(2) = 10 %.

Figure 26 and Figure 27show the estimated output power at THD = 0.5 % and THD = 10

% as a function of supply voltage for different load impedances in stereo mode.

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