ATAR080 datasheet(17/68 Pages) ATMEL

17 / 68 page

ATAR080

4675D–4BMCU–12/04

Figure 19. Ceramic Resonator

Note:

Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider cir-

cuit to stabilize oscillation before the oscillator output is used as system clock. This

results in an additional delay of about 4 ms for the 4-MHz crystal and about 500 ms for

the 32-kHz crystal.

32-kHz Oscillator

Some applications require long-term time keeping or low resolution timing. In this case,

an on-chip, low power 32-kHz crystal oscillator can be used to generate both the

SUBCL and the SYSCL. In this mode, power consumption is greatly reduced. The

32-kHz crystal oscillator can not be stopped while the power-down mode is in operation.

Figure 20. 32-kHz Crystal Oscillator

Note:

Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider cir-

cuit to stabilize oscillation before the oscillator output is used as system clock. This

results in an additional delay of about 4 ms for the 4-MHz crystal and about 500 ms for

the 32-kHz crystal.

Clock Management

The clock management register controls the system clock divider and synchronization

stage. Writing to this register triggers the synchronization cycle.

4-MHz

oscillator

4Out

Stop

4Out

Osc-Stop

OSC1

OSC2

Oscin

Oscout

Cer.

Res

32-kHz

oscillator

32Out

OSC1

OSC2

Oscin

Oscout

XTAL

32 kHz

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