PCA9541ADSLASH01 datasheet(18/45 Pages) NXP

18 / 45 page

PCA9541A

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Product data sheet

Rev. 5 — 24 April 2014

18 of 45

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

7.6 External reset

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst)L.

The PCA9541A registers and I2C-bus state machine are held in their default states until

the RESET input is once again HIGH. This input typically requires a pull-up resistor to

VDD.

Default states are:

• I2C-bus upstream Channel 0 connected to the I2C-bus downstream channel for the

PCA9541A/01

• no I2C-bus upstream channel connected to the I2C-bus downstream channel for the

PCA9541A/03.

7.7 Voltage translation

The pass gate transistors of the PCA9541A are constructed such that the VDD voltage can

be used to limit the maximum voltage that is passed from one I2C-bus to another.

Figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph

was generated using the data specified in Section 12 “Static characteristics” of this data

sheet). In order for the PCA9541A to act as a voltage translator, the Vo(sw) voltage should

be equal to, or lower than the lowest bus voltage. For example, if the main buses were

running at 5 V, and the downstream bus was 3.3 V, then Vo(sw) should be equal to or

below 3.3 V to effectively clamp the downstream bus voltages. Looking at Figure 8, we

see that Vo(sw)(max) is at 3.3 V when the PCA9541A supply voltage is 4.0 V or lower so the

PCA9541A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to

bring the bus voltages to their appropriate levels (see Figure 17).

More Information on voltage translation can be found in Application Note AN262:

PCA954X family of I2C/SMBus multiplexers and switches.

(1) maximum

(2) typical

(3) minimum

Fig 8.

Pass gate voltage as a function of supply voltage

VDD (V)

2.0

5.5

4.5

3.0

4.0

002aaa964

3.0

2.0

4.0

5.0

Vo(sw)

(V)

1.0

3.5

5.0

2.5

(1)

(2)

(3)

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