SMS64 datasheet(15/24 Pages) SUMMIT

15 / 24 page

SMS64

Preliminary

Summit Microelectronics, Inc

2060 2.22 10/09/03

COMMAND REGISTER

The command register (slave address 1001 [BIN]

software control of several functions in the SMS64

(see Figure 7). Each of these functions is activated by

writing a 1 to the function’s bit in the command register

(listed below). Only one command can be issued at a

time; therefore, only data bytes 80[HEX], 40[HEX], 20[HEX],

10[HEX] and 00[HEX] should be written to the command

cleared when power is removed.

Bit 7 is the power-on bit. When active it will initiate a

power-on sequence.

Bit 6 is the power-off bit. When active it will initiate a

power-off sequence.

Bit 5 is OR’ed with the FS# pin. When active it will

turn off all PUP outputs.

Bit 4 is OR’ed with the WLDI pin. When active it will

clear both the Longdog and Watchdog timers and

block interrupts.

FAULT and STATUS REGISTERS

The fault and status registers (see Figure 7) are

volatile registers which reflect the conditions of the VM

inputs.

In either register a fault condition (under-

voltage or over-voltage) is represented as a “1”.

The Fault register (located at register address 0D

[HEX]) latches the state of the VM inputs when an IRQ#

is generated.

The Status register (located at register address 0E

[HEX]) reflects the current state of the VM inputs.

CONFIGURATION REGISTERS

The SMS64 has 24 configuration registers that

allow programming voltage thresholds, timer values,

sequencing order and output configurations. All of

these registers are accessible over the I

2C serial

interface.

For prototyping purposes, Summit can provide a

programming cable (SMX3200) that interfaces a PC

parallel port to the serial interface of the SMS64 (see

the ‘Development Hardware and Software’ section).

Summit provides software that can be downloaded

from its website without charge.

The software

provides

intuitive

graphical

user

interface

comprised of drop-down menus that make selecting

options straightforward, thereby eliminating the need

to understand the register configurations in detail.

MEMORY ARRAY

The SMS64 has 4-K bits of nonvolatile memory

that is accessible over the 2-wire serial interface. This

memory can be used in a dynamic manner by the host

processor or it could be used to store board

configuration

information

board

identification

information. The slave address used to access the

memory can be configured as 1010 [BIN] or 1011 [BIN].

The memory array can be read whenever chip

select is enabled (CS# low). In order to prevent

inadvertent writes, memory writes are blocked when

either RST_A# or RST_B# are active. Therefore, the

memory can only be written after the device has

performed a power-on operation, the reset outputs

(RST_A# and RST_B#) have timed out and before the

device has been issued a force shutdown or power-off

command. MR# must also be high.

Command Register

1 = FS

1 = PWR_DOWN

1 = PWR_UP

1 = WLDI

UV/OV

Fault & Status Register

Figure 7 – Command and Status Registers

APPLICATIONS INFORMATION (CONTINUED)

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