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SMS44G bảng dữ liệu(PDF) 11 Page - Summit Microelectronics, Inc.

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SMS44G bảng dữ liệu(HTML) 11 Page - Summit Microelectronics, Inc.

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11
2047 2.3 10/23/00
SMS44
SUMMIT MICROELECTRONICS, Inc.
Table 8. Memory Operating Characteristics
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a “transmitter” and any device that receives data as
a “receiver.” The device controlling data transmission is
called the “master” and the controlled device is called the
“slave.” In all cases the SMS44 will be a “slave” device,
since it never initiates any data transfers.
2047 Table08 2.2
Figure 8. Memory Operating Characteristics
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time, because changes on the data line while SCL is high
will be interpreted as start or stop condition.
tF
tR
tLOW
tHIGH
tHD:STA
tSU:STA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
2047 Fig08 2.1
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