MPC5643L datasheet(21/136 Pages) NXP

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Introduction

MPC5643L Microcontroller Data Sheet, Rev. 10

NXP Semiconductors

The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO

5001-2003 Class 3+, including selected features from Class 4 standard.

The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the

MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also

supports a JTAG only mode using only the JTAG pins. The following features are implemented:

•

Full and reduced port modes

•

MCKO (message clock out) pin

•

4 or 12 MDO (message data out) pins1

•2 MSEO (message start/end out) pins

•EVTO (event out) pin

— Auxiliary input port

•EVTI (event in) pin

•

5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)

— Supports JTAG mode

•

Host processor (e200) development support features

— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool

to trace reads or writes, or both, to selected internal memory resources.

— Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility

of which process ID or operating system task is activated. An ownership trace message is transmitted when a

new process/task is activated, allowing development tools to trace ownership flow.

— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities

(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what

transpires between the discontinuities. Thus, static code may be traced.

— Watchpoint messaging (WPM) via the auxiliary port

— Watchpoint trigger enable of program and/or data trace messaging

— Data tracing of instruction fetches via private opcodes

1.5.39

IEEE 1149.1 JTAG Controller (JTAGC)

The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic

when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block

is compliant with the IEEE standard.

The JTAG controller provides the following features:

•

IEEE Test Access Port (TAP) interface with 5 pins:

—TDI

—TMS

—TCK

—TDO

—JCOMP

•

Selectable modes of operation include JTAGC/debug or normal system operation

•

5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

— IDCODE

1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.

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