MPC850EC datasheet(56/72 Pages) NXP

tên linh kiện	MPC850EC

Giải thích chi tiết về linh kiện	PowerQUICC??Integrated Communications Processor Hardware Specifications

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MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

CPM Electrical Characteristics

Figure 55. Ethernet Transmit Timing Diagram

8.8

SMC Transparent AC Electrical Specifications

Figure 21 provides the SMC transparent timings as shown in Figure 56.

Table 21. Serial Management Controller Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

150

SMCLKx clock period 1

The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.

100.00

—

151

SMCLKx width low

50.00

—

151a

SMCLKx width high

50.00

—

152

SMCLKx rise/fall time

—

15.00

153

SMTXDx active delay (from SMCLKx falling edge)

10.00

50.00

154

SMRXDx/SMSYNx setup time

20.00

—

155

SMRXDx/SMSYNx hold time

5.00

—

TCLKx

128

TxDx

(Output)

128

TENA(RTSx)

(Input)

NOTES:

Transmit clock invert (TCI) bit in GSMR is set.

If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the

CSL bit is set in the buffer descriptor at the end of the frame transmission.

RENA(CDx)

(Input)

133

134

132

131

130

129

(NOTE 2)

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